The present invention is directed to semiconductor devices and, more specifically, to semiconductor devices such as memory and switching circuits including thyristors.
Recent technological advances in the semiconductor industry have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Presently, single-die microprocessors are being manufactured with many millions of transistors, operating at speeds of hundreds of millions of instructions per second and being packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices have led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has also increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the design, construction, and manufacture of semiconductor devices, such as SRAM, DRAM, thin capacitively-coupled thyristor memory circuits, NMOSFETS and PMOSFETS, concerns the ability to accurately and efficiently define features within the devices. There are many types of such features including, for example, source/drain regions or gate stacks of transistors, bases or emitter regions or thyristors, and other device materials (e.g., resists, dielectrics and (semi)conductive layers) as used in processing semiconductor devices. One approach to feature definition includes patterning a photoresist mask over a substrate, directing ions at the substrate and using the mask to prevent portions of the substrate from being implanted with the ions. This type of feature definition often involves use of spacer material formed on a feature""s sidewalls to mask portions of the substrate below the spacers. However, photoresist patterning is sometimes non-uniform and difficult to control, and can result in asymmetric features due to misalignment and width variations of the photoresist. Such asymmetric results may include, for example, short circuits, open circuits and other circuit characteristics that affect the operation of the device in which the defined features are to be used.
Using spacers as symmetric structures around topological features, such as a gate stack and/or resist, would typically add, complexity to the process if device formation requires the spacer to be removed later in the process. Where such spacers are used with devices requiring finely-controlled asymmetric doping, a portion of the spacer might need to be removed to achieve the asymmetric doping; this removal step adds process complexity. In other applications, the horizontal dimension of a feature-surrounding pacer is used to shadow implant a doped region beyond the horizontal dimension of the spacer; however, this horizontal dimension is typically limited by the feature""s height dimension. To increase the horizontal spacer dimension, a combination of spacer and implant shadowing can be used. For applications that require doping various regions with different distances from respective features, using multiple spacers in an attempt to accomplish this result can lead to an unduly complex process. For example, such a process would involve multiple process steps of shadowed ion implants.
These and other considerations have presented challenges to implement a variety of circuits in bulk substrate applications, and in particular to high-density applications.
The present invention is directed to overcoming the above-mentioned challenges and others related to the types of devices and applications discussed above and in others. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor device is manufactured using ion implant shadowing to self-align features or structures therein. More specifically, doped substrate portions of the semiconductor device are formed using an angled ion implant and features defined on a surface of the substrate, with the surface features masking a portion of the substrate. The height of the surface features and the angle of the ion implant are selected and used to define the extent that substrate portions adjacent to the surface features are masked, and thus determine which portions of the substrate are implanted. With this approach, variation in the width of doped regions in the substrate is set as a function of parameters including the height of features used to mask the substrate and the ion implant angle.
In another example embodiment of the present invention, a memory cell includes a thyristor having a base region thereof in a substrate and aligned to a feature on an upper surface of the substrate. An angled implant is used, in connection with the feature, to space the base region at a selected distance from the feature (e.g., with the space between the feature and the base region being increased with smaller implant angles).
In another example embodiment of the present invention, two or more ion implants are carried out from different directions over a substrate for implanting regions in the substrate spaced at different distances from a surface feature on the substrate. A first ion implant is carried out from a first direction (e.g., left-to-right) and at a first angle, resulting in a portion of the substrate being doped on a first side of the surface feature. A second ion implant is then carried out from a second direction that is different than the first direction (e.g., right-to-left) and at a second angle, resulting in a portion of the substrate being doped on a second side of the surface feature that is opposite the first side. In one implementation, the first and second ion implant angles are the same, relative to the substrate, and in another implementation, the first and second ion implant angles are different.
In another example embodiment of the present invention, two or more features are defined on an upper surface of a substrate and at different heights selected for subsequent ion-implant alignment. An angled ion implant is carried out, with the two or more features being used to mask a portion of the substrate. The different heights of the two or more features results in implanted regions adjacent to each of the two or more features having different spacing from the two or more features. For instance, an implanted region adjacent to a high feature is spaced at a greater distance from the high feature than the spacing of an implanted region adjacent to a relatively lower feature.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.